
36 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS
The corresponding real layout (after flattening) is shown in Figure 1.16.
Figure 1.16: The real layout of our mux shown by DREAL.
1.7 DRUC
DRUC (Design RUle Checker) is the Alliance parametrized VLSI design rule checker. The rules it uses are
defined by the RDS TECHNO NAME environment variable. DRUC flattens all the hierarchy of the design to
check if there is any violation to the specified design rules, so when applying it is necessary to assure that root
and instantiated cells are in the current directory. Let’s apply DRUC to our muxoor.ap design file to check it.
% druc -v muxoor
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Design Rule Checker
Alliance CAD System 5.0 20040928, druc 5.0
Copyright (c) 1993-2005, ASIM/LIP6/UPMC
Flatten DRC on: muxoor
Delete MBK figure : muxoor
Load Flatten Rules : /usr/local/alliance/etc/cmos.rds
layer RDS_NWELL 4.;
layer RDS_NTIE 2.;
....intermediate output has been deleted for space reasons.
fin regles
Unify : muxoor
Create Ring : muxoor_rng
Merge Errorfiles:
Merge Error Instances:
instructionCourante : 56
End DRC on: muxoor
Saving the Error file figure
Done
0
File: muxoor.drc is empty: no errors detected.
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