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24 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS

pages), shows the use of resolved and guarded signals.

begin first_driver_of_mux : block (Sel1 = ’1’) begin

Distributed_Mux <= guarded Data1; end block;

second_driver_of_mux : block (Sel2 = ’1’) begin

Distributed_Mux <= guarded Data2; end block;

We can use sequential statements but their sequential elements must be explicitly declared using the type reg bit

or reg vector and be of type register. Also, a sequential element must be assigned inside a block statement by

a guarded assignment. An example showing this type of statements is shown in the following edge-triggered

ﬂip-ﬂop description.

begin

Reg <= guarded Din;

end block;

One more example (also taken from the man pages) is the following level sentitive latch description.

begin

Lat <= guarded Din;

end block;

If we intend to use the b ehavioral description during the logic synthesis process, we must assure that the

guarded signal depends on only one signal (as in the above examples). In the subset supported by Alliance only

the logical operators ( not, and, or, xor, nor, and nand), concatenation (&), equality (=), and nonequality

(/ =) are supported. Arithmetic (+ and −), comparison (<, >) and all other operators (mod, <= ∗∗, etc.)

are not supported in Alliance. As indicated before, timing information is supported using after clauses. But

they can not be used in sequential s tateme nts (those handling signals of type register). However they can be

used with signals of kind bus. They can also be used in selected s ignal assigments provided they have the

same after clause (same delay). The transport option is not allowed in the subset handled by Alliance. In the

assert statement only two levels of severity are supported. One is warning that prints a message if the assert

condition is not satisﬁed. The other is error that prints an error message an stops the simulation. In Alliance is

also possible to use D as don’t care value for synthesis purposes but we must be careful since it is not a VHDL

standard supported value. During simulation D is replaced by 0 by ASIMUT. The only array types supported

in Alliance are those listed in Table 1.2.

1.2 B2F

The B2F (Behavior to Finite state machine format abstractor) tool is a translator from a behavior description

to a FSM (Finite State Machine) format. It uses as input a RTL (Re gister Transfer Level) VHDL description

(in the behavioral subset used in Alliance) in .vbe format. This tool uses a symbolic simulation algorithm to

build a graph equivalent to the target ﬁnite state machine that is given as output. We drive the tool giving the

following command.

% b2f [options] input_file output_flle

The options of B2F are shown in Table 1.4. Table 1.4. Let’s see one example of use of this tool. For this, we

Table 1.4: Options Available for the B2F Tool.

Option Description

-V

Sets Verbose mode on

-I bit string Initial value of the state register

-O o0,...,on

Initial value (one index list)

-Z z0,...,zn

Initial value (zero index list)

-R reset cond Reset condition

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 86 87

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