ADDER X-SC Bedienungsanleitung Seite 14

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14 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS
Every input pattern file has the following general format:
-- description of the input and outp ut ports : terminal_type terminal_name logic_type ;
-- use B for binary values, O for octal ones and X for hexadecimal values.
-- source and ground terminals
in vdd B;
in vss B;
-- other input and output ports of the circuit
-- the input values and expected out puts by time interval
-- <time> [description] : input_values_ in_ the_order_given_above expected_value(s) ;
-- output values are preceded by a ?
-- we write the expected values afte r it ex. ?1 or ?0
-- if one wants the simulator to calculate an output value we indicate it with ?*
begin
<0 ns> initi al_ valu e : 10 00 ?*;
<+1 ns> next_interval : 10 0 0 ?*;
end;
Here lines starting with −− indicate a comment line. Following the above guidelines we can write the input
pattern file mux in.pat of the multiplexer circuit as follows:
-- terminals of the mux circuit
in vdd B;
in vss B;
in c B;
in a B;
in b B;
out q B;
-- time interval description of the i nput values and expected (undetermined) output
begin
<0 ns> mux_test : 10 000 ?*;
<+1 ns> notc_nota_notb : 10 000 ?*;
<+1 ns> notc_nota_b : 10 001 ?*;
<+1 ns> : 10 001 ?*;
<+1 ns> notc_a_notb : 10 010 ?*;
<+1 ns> : 10 010 ?*;
<+1 ns> notc_a_b : 10 011 ?*;
<+1 ns> : 10 011 ?*;
<+1 ns> c_nota_notb : 10 100 ?*;
<+1 ns> : 10 100 ?*;
<+1 ns> c_nota_b : 10 101 ?*;
<+1 ns> : 10 101 ?*;
<+1 ns> c_a_notb : 10 110 ?*;
<+1 ns> : 10 110 ?*;
<+1 ns> c_a_b : 10 111 ?*;
<+1 ns> : 10 111 ?*;
end;
As shown inn this file, we has written an input pattern file for all the possible combinations of the input values.
We start with 00 at time 0 and then at 1ns intervals we modify the input values to test the circuit for all its
possible input combinations. We can visualize these patterns using xpat (see section 1.30) giving the following
command line and opening mux in.pat from the file menu of this graphic tool.
% xpat &
The opened file will display the input signal and undetermined output signal as shown in Figure 1.3. With
this input pattern file we can now run ASIMUT and make it compile the circuit and its input pattern file and
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