
1.1. ASIMUT 21
indicate that both, delay and area must be optimized. The corresponding output will be as follows.
% boog invg_o invg -x 1 -m 2
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Binding and Optimizing On Gates
Alliance CAD System 5.0 20040928, boog 5.0 [2003/01/09]
Copyright (c) 2000-2005, ASIM/LIP6/UPMC
Author(s): Fran?ois Donnet
MBK_VDD : vdd
MBK_VSS : vss
MBK_IN_LO : vst
MBK_OUT_LO : vst
MBK_WORK_LIB : .
MBK_TARGET_LIB : /usr/local/alliance/cell s/s xlib
Reading default parameter...
50% area - 50% delay optimization
Reading file ’invg_o.vbe’...
Controlling file ’invg_o.vbe’...
Reading lib ’/usr/local/alliance/cells/s xlib ’...
Mapping Warning: Cell ’halfadder_x4’ isn’t supported
Mapping Warning: Cell ’halfadder_x2’ isn’t supported
Mapping Warning: Cell ’fulladder_x4’ isn’t supported
Mapping Warning: Cell ’fulladder_x2’ isn’t supported
Controlling lib ’/usr/local/alliance/cel ls/s xlib ’...
Preparing file ’invg_o.vbe’...
Capacitances on file ’invg_o.vbe’...
Unflattening file ’invg_o.vbe’...
Mapping file ’invg_o.vbe’...
Saving file ’invg.vst’...
Quick estimated critical path (no warranty)...116 ps from ’a’ to ’q’
Quick estimated area (with over-cell routing)...750 lambda?
Details...
inv_x2: 1
Total: 1
Saving delay gradient in xsch color file ’invg.xsc’...
End of boog...
We give the same command for the other two gates andg o, and org o. These will give us with the .vst files
corresponding to our leaf designs. Check it as follows.
% ls *.vst
andg.vst inv.vst invg.vst mux.vst org.vst
Once we have all these files we can now simulate our structural description of the mux using ASIMUT as
follows.
% asimut mux mux_in muxst_out
We are using here the input patterns we used for testing our behavioral description, and we are now saving the
generated patterns files in a muxst out.pat file. We can use this file to compare the outputs obtained with
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