ADDER X-SC Bedienungsanleitung PDF herunterladen (Seite 18)

18 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS

Table 1.2: Set of types used in the VHDL subset of Alliance.

Type Description

bit

The standard bit type: ’0’ or ’1’

bit vector

Array of bits

mux bit

Resolved subtype of bit using the mux resolution function. This function checks

that only one driver is actually connected to a signal. The eﬀective value of the

signal is the value of the active driver. If all drivers are disconnected, the value of

the signal is ’1’ (pullup). A signal of type mux bit must be declared with the kind

bus.

mux vector

Array of mux bit

wor bit

Resolved subtype of bit using the wor resolution function. This function allows a

signal be driven by more than one drive r. All active drivers have to drive the same

value. The eﬀective value of the s ignal is the value of active drivers. If all drivers

are disconnected, the value of the signal is ’1’ (pull up). A signal of type wor bit

must be declared with the kind bus.

wor vector

Array of wor bit

reg bit

Resolved subtype of bit using the reg resolution function. This function checks that

only one driver is actually connected to a signal. The eﬀective value of the signal

is the value of the active driver. A signal of type reg bit must be declared with the

kind register (which makes the signal keep its previous value when all drivers are

disconnected).

reg vector

Array of reg bit

is described using port mapping. We can do explicit and implicit port mapping. However unconnected ports

are not allowed. Moreover, only the concatenation operator & can be used in port mapping. Let us see an

example using the multiplexer circuit of the previous section. For this we will use the following leaf AND gate.

-- AND gate entity andg is port(a : in bit;

b : in bit;

q : out bit;

vdd : in bit;

vss : in bit); end andg;

architecture vbe of andg is begin

q <= (a AND b); end vbe;

And, the following leaf OR gate design.

-- OR gate entity org is port(a: in bit;

b: in bit;

q: out bit;

vdd: in bit;

vss: in bit); end org;

architecture vbe of org is begin

q <= (a OR b); end vbe;

And the following leaf NOT gate design.

-- inverter (NOT) gate entity invg i s port(a : in bit;

x : out bit;

vdd : in bit;

vss : in bit); end invg;

architecture vbe of invg is begin

x <= NOT(a); end vbe;

We will combine these gates as shown in Figure 1.6. The corresponding structural VHDL ﬁle is as follows.

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