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1.1. ASIMUT 23

ﬂow).

% env | grep MBK

MBK_IN_LO=vst

MBK_OUT_LO=vst

MBK_IN_PH=ap

MBK_OUT_PH=ap

MBK_WORK_LIB=.

MBK_CATAL_NAME=CATAL

MBK_SCALE_X=100

MBK_CATA_LIB=.:/usr/local/alliance/cells/sxlib:/usr/local/alliance/cells/dp_sxlib:

/usr/local/alliance/cells/rflib:/usr/local/alliance/cells/romlib:/usr/local/alliance/cells/ramlib:

/usr/local/alliance/cells/padlib

MBK_TARGET_LIB=/usr/local/alliance/cells/sxlib

MBK_C4_LIB=./cellsC4

MBK_VDD=vdd

MBK_VSS=vss

We will not detail them here, but notice that MBK IN LO is set to vst, in this case the default format expected

by ASIMUT. The design ﬂow using ASIMUT up to this point is shown in Figure 1.7. Details of the behavioral

Figure 1.7: Basic structural simulation using ASIMUT.

subset supported by the Alliance tools are given in the following subsection.

1.1.1.2 Behavioral VHDL Subset

In many cases we do not need to specify the structure of the design but its function. In this case we make no

reference to the internal structure of the design entity. Such a description of the design is called functional or

behavioral. We have already seen the behavioral description of three basic gates (the AND, OR and NOT gates

of the previous subsection) and of a multiplexer. In those small designs it is possible to describe the behavior

of the circuits as functions of their inputs. However more complex circuits require other types of descriptions.

VHDL provide many means for des cribing complex behaviors, but Alliance supports only part of them. In the

subset supported by Alliance only c oncurrent statements are allowed in the behavioral description. Also, we

can not use sequential stateme nts (loops, etc.) or processes. Timing information is allowed in the behavioral

description using after clauses. However, these delay values are used only in the simulation of the design and

not in the synthesis or formal proof stages. The allowed c oncurrent statements in the subset of Alliance are

shown in Table 1.3.

Table 1.3: Concurrent Statements in the VHDL Subset of Alliance.

Type Example

simple signal assignment q <= a and b;

conditional signal assignment q <= D when clock = ’1’ and E = ’0’;

selected signal assignment

with expression select

target <= value1 when choice1, value2 when choice2;

concurrent assert statement

assert Reset = ’1’;

block statement

clump : block begin A <= B or C; D <= B and not C; end

block clump ;

When using concurrent statements, we must assure that an ordinary signal is assigned only once. Also, the

signal value must be explicitly deﬁned by the signal assignment. When using selected signal assignment we

must ensure that the target value is deﬁned for every value that the select expression can take. The restrictions

that could arise from this limited set of s tatements is relaxed through the use of resolved signals (see the VHDL

section). We can also use guarded signals. The following example, a bus with two drivers (taken from the man

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