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Introduction to CMOS VLSI Design (E158)

Harris

Project 1

The goal of this project is to design a 10-bit adder with the lowest energy × delay

product.s

Block Specification

Function: module adder(input clk,

input [9:0] a, b,

output [9:0] y);

assign y = a + b;

endmodule

Inputs: each driven by two buf_1x cells from muddlib, changing concurrently with clk

Outputs: each must drive an inv_4x cell from muddlib

Objective: minimize the power × delay product of the adder (including the power

drawn from V

by the input buf_1x cells and the power consumed by the

inv_4x output loads)

Simulation Environment

Simulate the chip using the AMI 0.5 μm process with λ = 0.3 μm. Assume an on-chip

temperature of 70

◦

C. You may choose one or more DC supply voltages between 1.2 and

5 V. You may also choose the clock period.

Several files are included in /courses/e158/10/proj1 to help

adder_ripple: library containing a 10-bit ripple carry adder

addertest.v: Verilog test bench

adder.tv: limited set of testvectors for Verilog testbench

testbench.sp: HSPICE test bench with code to measure delay and energy

tc.sp desired cycle time (isolated from testbench for ease of changing)

stim.vec: digital vector file with limited set of testvectors for SPICE testbench

cycletime.pl: a Perl script to repeatedly run HSPICE to find the minimum delay

1 2 3 4 5

Inhaltsverzeichnis

Seite 1 - Project 1

Introduction to CMOS VLSI Design (E158)HarrisProject 1 The goal of this project is to design a 10-bit adder with the lowest energy × delay product.s

Seite 2 - HSPICE Simulation

Read through each of these files so you understand how they work. It is recommended that you work from adder_ripple and replace the ripple carry adder

Seite 3 - Deliverables

Modify the stim.vec file to include your actual test vectors. Check that the ripple carry adder still works (at a sufficiently slow cycle time) to v

Seite 4

On the last day of the project (March 9), you will be given a new mystery set of test vectors. Once you have viewed these vectors, you may make no fu

Seite 5 - Grading

Grading Your grade will be based on the following factors: 30%: Readable schematics simulating on schedule 5%: Convincing test vectors 30%: Claimed

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