Read through each of these files so you understand how they work. It is recommended
that you work from adder_ripple and replace the ripple carry adder with something better.
You are free to use cells from muddlib or to invent new cells.
Run your Verilog simulation in the same way that you did in Lab 4, using addertest.sv as
the testbench.
HSPICE Simulation
HSPICE simulation involves generating a netlist from your schematic, modifying the
testbench to point to your schematic, setting your target cycle time, setting your vectors,
and running the simulator. You may optionally use a Perl script to automatically
determine the minimum cycle time at which the circuit operates correctly on the vectors
provided.
Create a new directory for your simulation (e.g. ~/proj1). Copy all the SPICE-related
files from the course proj1 directory.
The first step is to generate a netlist of your schematic. A good plan is to start with the
adder_ripple schematic provided so that you can test that everything works. In the
schematic editor, choose Tools • Analog Environment. An Analog Design Environment
window will open. Choose Setup • Simulator. Set the simulator to HSPICE (not
hspiceD). Choose a project directory for the netlist; ~/cadence/simulation is fine. Then
choose Simulation • Netlist • Recreate. Look at the netlist in the window that opens and
check that it looks reasonable.
Next, go into the simulation directory. Read through testbench.sp and see how it works.
Check that it points to the correct directory where your netlist was created. Look at
stim.vec and see the default vectors. The first cycle is potentially for reset and is not used.
The expected output is checked one cycle after the inputs are applied. XXX indicates
don’t care for an output. Edit tc.sp and change the cycle time to something conservative,
such as 20 ns.
Run the simulation by typing
hspice testbench.sp > testbench.lis
The results will appear in the .lis file. The measurement results are also summarized in
the .mt0 file. The simulation waveforms are in the .tr0 file where you can inspect them
with Spice Explorer (sx). The .err file indicates whether there were any discrepancies
with the expected outputs in the .vec file. If the file is empty, there were no errors.
Shorten tc.sp and rerun the simulation. Check if there are any errors in testbench.err.
Repeat this process until you find the minimum cycle time at which the ripple carry adder
works (it should be about 9.4 ns). Check the measured energy and compute the energy-
delay product.
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